As device dimensions decrease and device densities increase, chip performance degrades due to signal delays and cross talk between the conductor lines. Signal propagation delays are characterized by the product of metal resistance (R) times the capacitance (C) of the lines (RC delay), which has the dimension of time in seconds. The RC delay depends on the resistivity of the wiring metallurgy, the dielectric constant(s) of the insulating media, and the dimensions and configuration of the metal lines. The relatively recent change in metallurgy from aluminum to copper has reduced the resistivity of the metal by about 30%, providing a significant improvement in performance. However, the RC delay phenomenon is exacerbated by the high polarizability of conventionally integrated SiO2 (k˜4) dielectric and the need to keep conductor lines as short as possible. While the switch to copper metallurgy and new multilevel wiring schemes have ameliorated the RC delay problem, as feature sizes go below 0.25 μm, this alone will not provide a solution.
The use of an insulator with a dielectric constant (k) lower than SiO2 would reduce parasitic capacitance and crosstalk, but it must still meet a number of stringent integration requirements including: thermal stability ≧400° C., resistance to crack generation and propagation, low defect density, low water uptake, chemical resistance, processability by photolithographic techniques and gas-phase etching, as well as a capacity for chemical mechanical planarization (CMP). Inorganic insulators may satisfy most of these requirements, however, extendibility to future device generations requires the introduction of porosity (e.g., k=1 for air) to lower the dielectric constant.
Porous low-k materials have been introduced for use in specialty ICs over the last several years. The porous materials exhibit dielectric constants from about 2.5 to about 3.0, but unfortunately exhibit low-moduli, are prone to cracking, and mostly contain interconnected pores, which makes subsequent processing steps such as electroplating and CMP more difficult. Because of these drawbacks, there is a need for fully dense materials, such as low-k PHTs, with improved properties that do not suffer from the disadvantages of porous low-k materials in IC applications.
New generation printed circuit boards (PCBs) used in high speed (>2 Gb/s) telecommunication equipment and internet infrastructure servers face a similar challenge as ICs due to decreasing device and substrate dimensions. PCBs increasingly put more function in a smaller space, which requires more components, while utilizing smaller bond pads, smaller lines and tighter pitch. The shrinking form factors combined with the future integration of optical signal transmission in 3D packaging schemes has driven the need for lower dielectric constant printed circuit board substrates. Because of the new PCB challenges, it would be an advantage to replace high k epoxy matrix resins used in PCBs (e.g., FR-4 type), with new low-K PHTs to reduce crosstalk and parasitic capacitance.